This invention relates, generally, to an integrated circuit ceramic substrate interface and more particularly to the hermetically sealing of the interface.
There is a continuing need in industry as well as military for chip carriers which are reliably and inexpensively hermetically sealed. This need for hermetic sealing is quite important since a minimum of moisture which may leak into a package is extremely troublesome and expensive to diagnose and repair. A number of methods have been tried, one of which is found in U.S. Pat. No. 4,355,463, "Process for Hermetically Encapsulating Semi-Conductor Devices" issued Oct. 26, 1982 to Burns. Traditional methods of hermetic sealing have required that the chip carrier and the IC chip contained therein be elevated to temperatures which will melt glass which is typically the sealing or gasket material. However, this presents a multitude of problems in addition to the potential high temperature problems which may damage the IC chip. These problems relate to glass breakage during thermal cycling which thereby breaks the seal, adhesion problems between the lead frames utilized and the substrate upon which they are deposited on, or the generation of water as a by-product.
Therefore, it is desirable to have a hermetically sealable chip carrier which is relatively inexpensive and which forgoes the high temperature processing of present techniques. Additionally, it is also desirable to have a device which does not use glass and does not experience water problems associated with high temeraptures. Such a device is taught by the present invention.
Accordingly, the present invention teaches and as an object of the present invention, a hermetic chip carrier comprising a substrate, a chip disposed on the substrate, inner leads disposed on the substrate on the same side as the chip, a sealing ring disposed on the same side of the substrate as the chip, outer leads disposed on the substrate on the side opposite the chip in a pattern corresponding to the inner leads, a pedestal disposed in vias in the substrate, the pedestal electrically interconnecting the inner leads to corresponding outer leads, the outer leads being disposed on the substrate on the side opposite the chip and a diaphragm having a sealing skirt attached thereto wherein the sealing skirt is disposed on and attached to the sealing ring.